This invention relates to an over-current protection apparatus for an insulated gate controlled transistor such as a power MOS transistor, an insulated gate bipolar transistor, etc. Because the power MOS transistor is applicable in a high frequency range and the insulated gate bipolar transistor is well suited for large current applications due to its output impedance, these insulated gate controlled transistors, with their exceedingly high input impedance, are widely used in a vertical element of a switching power supply, an inverter for controlling a motor, etc.
However, the power transistor requires some protection measures against an over-current since the power transistor is damaged or broken down rather easily by the over-current caused by abnormality on the load side. Currently, protection measures have been incorporated into an integrated circuit together with related circuits. A protection scheme has been known which incorporates a current detector transistor as an over-current protection means for a main transistor. The current detector transistor protects the main transistor by detecting an over-current flowing through the main transistor based on the principles of the Miller current circuit. This protection scheme is described, for example, in Electro mini/micro Northeast Conf. Rec. E 10.4.1-10.4.4., 1986 by D. L. Zaremba Jr. and in the U.S. Pat. No. 4,783,690. FIG. 6 schematically shows the protection technique according to the prior art.
In FIG. 6, a load power supply 2 usually supplies voltage of several hundred volts to a load 1. A main transistor 10 which controls a current flowing through the load 1 is a power MOS transistor, the drain terminal D of which is connected with the load 1 and the source terminal S of which is grounded. The main transistor 10 is usually comprised of many unit structures connected in parallel with each other and repeatedly incorporated into a semiconductor apparatus. A current detector transistor 20 is comprised of from one to several unit structures, assigned to the current detection purpose, having the same unit structure with that of the main transistor 10 and being incorporated into the semiconductor apparatus. As FIG. 6 shows, the drain and the gate of the current detector transistor 20 are connected in common to the drain and the gate of the main transistor 10, respectively. The common gate receives a drive command Ss from a drive circuit 3. Usually, a gate resistance Rg is connected as shown in FIG. 6 to the common gate for adjusting the switching speed of transistor 10 controlling the current supplied to the load 1.
According to the principles of the Miller current circuit, a small follower current i of one several thousandth of a reference current I of the main transistor 10 flows through the current detector transistor 20. The follower current i is detected as a voltage drop across a current detecting means Rd connected to the source of the current detector transistor 20. An operational amplifier 30 compares a detection signal Vd indicative of the voltage drop with reference voltage Vr and outputs a comparison signal Sd indicative of a result of the comparison to a gate control circuit 40. The control circuit 40 outputs a control signal Sc to the common gate of the transistors 10 and 20 based on the comparison signal Sd.
When an over-current flows through the main transistor 10, the detection signal Vd exceeds the reference voltage Vr and the control circuit 40 which receives the comparison signal Sd from the operational amplifier 30 outputs the control signal Sc to the main transistor 10 to limit or shut off the current I flowing through the main transistor 10. When the drive circuit 3 designates ON and OFF of the main transistor 10 by HIGH and LOW of the drive command Ss, the control signal Sc lowers the HIGH signal or changes the HIGH signal to the LOW signal.
The over-current protection apparatus according to the prior art protects the main transistor from an over-current by correctly detecting the current I of the main transistor 10 by means of the current i of the detector transistor 20 based on the principle of the Miller current circuit. However, oscillation tends to occur in the prior art circuit when the main transistor is of large current capacity, the electrostatic capacitance of which is large. This is because, though the feedback control system including the operational amplifier 30 and the control circuit 40 shows quick response and high gain, the controlled system including the gate capacitance and the gate resistance Rg of the main and current detector transistors 10 and 20 cannot quickly follow the control signals Sc.
The simplest measure for preventing the oscillation is to lower the responsiveness and the gain of the feedback system. However, this preventive measure causes insufficient over-current detection sensitivity and an excessively slow protective operation both of which cause damage or breakdown of the main transistor 10. The other measure for solving this problem has been to provide the operational amplifier 30 with a phase compensation function (see for example "Circuit Techniques For Fully Utilizing Operational Amplifiers" by Iwao Sagara, pp. 14-15, published in 1987 from Nikkan Kougyou). This phase compensation technique will be briefly explained below with reference to FIG. 7.
The operational amplifier 30 illustrated in FIG. 7 is comprised of a differential input block 31 which receives the detected voltage Vd and the reference voltage Vr, an amplifying block 32 which receives output of the differential input block 31, and an output block 33 which is driven by the amplifying block 32 and outputs the comparison signal Sd. A phase compensation capacitor Cp is connected, for example, on the input side of a transistor of the amplifying block 32 as shown in the figure. The phase compensation capacitor Cp shifts the phase of change of the comparison signal Sd corresponding to a change of the detected voltage Vd. The oscillation is prevented, without the deteriorating protective function, by appropriately adjusting the phase delay to match the response delay caused by the gate capacitance of the main transistor 10 of the controlled system.
In applying this compensation method to a practical circuit, it is difficult to adjust the capacitance of the phase compensation capacitor Cp to the characteristics of the controlled system, especially when adjustment of the gate resistance Rg is required depending on the load 1. Further, the capacitance of the phase compensation capacitor Cp becomes large in relation to the increase of the main transistor's current capacity. The compensation capacitance increase requires so wide a chip area for incorporating the capacitor Cp into the integrated circuit that the practical applicability of the phase compensation method is lost and the over-current protection function is lowered due to deterioration of the response of the operational amplifier 30.
In view of the foregoing, it is desirable to have an over-current protection apparatus for a transistor which is free from oscillation, well suited for practical use, and simply configured.